Architectural Techniques to Enhance DRAM Scaling

For decades,mainmemory has enjoyed the continuous scaling of its physical substrate: DRAM(DynamicRandomAccessMemory). But now,DRAMscaling has reached a thresholdwhereDRAMcells cannot bemade smaller without jeopardizing their robustness. This thesis identifies two specific challenges to DRAM scaling, and presents architectural techniques to overcome them. First, DRAMcells are becoming less reliable. AsDRAMprocess technology scales down to smaller dimensions, it is more likely for DRAM cells to electrically interfere with each other’s operation. We confirm this by exposing the vulnerability of the latest DRAM chips to a reliability problem called disturbance errors. By reading repeatedly from the same cell in DRAM, we show that it is possible to corrupt the data stored in nearby cells. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We provide an extensive characterization of the errors, as well as their behavior, using a custom-built testing platform. After examining various potential ways of addressing the problem, we propose a low-overhead solution that effectively prevents the errors through a collaborative effort between the DRAM chips and the DRAM controller. Second, DRAM cells are becoming slower due to worsening variation in DRAMprocess technology. To alleviate the latency bottleneck, we propose to unlock fine-grained parallelism within a DRAM chip so that many accesses can be served at the same time. We take a close look at how a DRAM chip is internally organized, and find that it is divided